Conventional practice in the manufacture of circuit chips involves the fabrication of semiconductor wafers having an array of devices comprising individual circuit elements formed on one surface of the wafer. The wafers are separated into discrete circuit chips or die by a diamond saw or other dicing equipment after the wafer has been mounted onto a wafer handling tape. The wafer tape having an adhesive on one surface is affixed to a film frame. The tape and frame secure the wafer during dicing, and provide a transport support through the chip mount process. Individual chips are removed from the tape by an ejector assembly on the chip mount equipment, and are placed on a receiving pad of a lead frame or on a metal pattern formed on an insulating substrate. The lead frame and metal pattern are the electrical contact to the next level of interconnection in the packaging system.
As illustrated in FIG. 1, a typical chip mount apparatus includes an x/y moveable table 10, which supports the handling tape 121 and frame 12 onto which a wafer 11 diced into a plurality of individual chips 111 is positioned, an ejector assembly 13 including a rigid support surface 131 larger than the chip size, an ejector motor 132, and one or more ejector pins 133. In operation, the selected chip 111 is centered atop the support surface 131 and ejector assembly 13, vacuum is applied to the tape, and ejector pins 133 are activated to cause the chip 111 to be raised vertically from the tape. A pick-up arm 14 secures the freed chip 111 and places it onto an awaiting interconnect medium (not shown).
Each individual chip 111 is removed from the tape by ejector pins 133 pressing upward against the back side of the rigid chip on flexible tape 121 while the tape is pulled downward by suction applied through vacuum apertures in the support surface 131. The support surface 131 includes a plurality of grooves with vacuum apertures through which the tape is to be pulled against the surface when vacuum is applied to the tape through the apertures. The rigid, nearly flat surface of the support surface 131 is typically referred to as a “dome”, as it will be hereafter in this disclosure.
As circuits have increased in complexity, chip sizes have increased and often wafer thickness has decreased, thus increasing sensitivity to various stress related defects. For almost all semiconductor devices speed and performance requirements have continuously become more demanding. Some semiconductor devices have a relatively small active circuit area, but the number of I/O (input/output) contacts is large, and in order to meet the speed and performance requirements, it is advantageous to position the bonding pads along the long sides of a high aspect ratio chip, allowing interconnect routing and bond wire lengths to be short. DRAM chips traditionally have high length to width ratios with leads and bonds predominately along the long axes, but more recently extremely high aspect ratio chips have been fabricated having a length to width ratio of about four or greater to one. Assembly of such devices without damage through dicing and pick and place processes presents a difficult challenge.
The ejector pin system for chip pick-up and place has been the source of a number of reliability and yield failures for many integrated circuit devices. The pins are sharp needle shaped devices which extend about 1 mm from the dome surface during ejection. The non-uniform contact between the pin and chip backside contributes to stress related defects on the chip backside as a result of mechanical contact by the ejector pins. Further, stresses from height variations of multi-needle ejectors, defective ejector pins, as well as tape or adhesive contamination on the chip from the sharp pointed or defective needles cause circuit failures. Stress related issues may result not only in cracked die, but also in latent defects detected only after thermal exposure during assembly or operation. Contamination from tape or adhesive being transferred to the chip backside may manifest itself as an uneven stress on the chip after assembly, or as a form of contamination contributing to corrosion or leakage. Yield losses may occur from damaged chips, or chips poorly placed on a receiving pad as a result of non-planar or tilted pick-up.
Small chips are ejected from the tape by a single needle, but large chips and high aspect ratio chips are typically pushed from the tape by multiple needles which are intended to distribute the stress load. However, it is time consuming and costly to hold precise tolerances between multiple tip heights, and during operation the sharp tips become damaged, resulting in height variation.
FIG. 2 provides a side view of an arrangement with three ejector pins 233 and 234 pushing a rectangular chip 211 from the handling tape 221. It can be seen in this illustration that the pins 233 and 234 are not at the same elevation. Specifically, the tip of the center pin 234 is extended further from the ejector dome 231 than the side pins 233, thereby allowing a stress concentration on the chip center which may result in a crack 212. In another example a needle placed at the end of a row may be lower than the others causing pick-up to be non-planar and result in misplacement of the chip on its receiving pad.
A need exists in the semiconductor industry for a process whereby large or high aspect ratio chips can be transferred from a handling tape precisely and without damaging the chip.